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136 IP
51
1.0
USB 2.0 PHY I/O in GF40nm
The Arasan Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses Arasan’s MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the US...
52
1.0
USB 2.0 PHY SMIC 130
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
53
1.0
USB 2.0 PHY TSMC 40LP
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
54
1.0
USB 2.0 PHY TSMC 55LP
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
55
1.0
USB1.1 PHY - HHGrace 110nm ULL
...
56
1.0
USB1.1 PHY - HHGrace 110nm ULL
...
57
1.0
USB1.1 PHY - SMIC 180nm
...
58
1.0
USB1.1 PHY - SMIC 180nm Logic
...
59
1.0
USB1.1 PHY - SMIC 180nm Logic
...
60
1.0
USB1.1 PHY - SMIC 55nm Eflash
...
61
1.0
USB1.1 PHY - SMIC130nm Eflash
...
62
1.0
USB1.1PHY controller
...
63
1.0
USB2.0 OTG PHY
...
64
1.0
USB2.0 PHY - SMIC 153nm Logic
...
65
1.0
USB2.0 PHY - SMIC 180nm Logic
...
66
1.0
USB2.0 PHY - SMIC130nm Eflash
...
67
1.0
USB3.0 PHY - SMIC 55nm Eflash
High speed analog circuits for USB3.0 PHY application 745um*620um...
68
1.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
69
0.118
USB 1.1 PHY IP, UMC 0.13um LL/FSG process
USB 1.1 transceiver, UMC 0.13um LL Logic/FSG process....
70
0.118
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 PHY, UMC 0.18um GII Logic process 1.8/3.3V....
71
0.118
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 transceiver, UMC 0.18um GII Logic process....
72
0.118
USB 1.1 PHY IP, UMC 0.5um Logic process
USB 1.1 PHY, UMC 0.5um Logic process 3.3V 1P3M....
73
0.118
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process
USB 1.1 transceiver support crystal-less mode in USB system ; UMC 55nm eFlash Process...
74
0.118
USB 2.0 Device PHY IP, Non-Crystal mode support, HJTC 0.11um pFlash/LL process
USB2.0 PHY, crystal-less, HJ 0.11um pflash LL process....
75
0.118
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 0.11um HS/AE process
Crystal-Less USB2.0 PHY, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
76
0.118
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
USB 2.0 PHY, crystal-less option, UMC 40nm LP/RVT process....
77
0.118
USB 2.0 Device PHY IP, UMC 0.11um eFlash process
UMC 0.11um eFlash Process , USB 2.0 OTG PHY...
78
0.118
USB 2.0 Device PHY IP, UMC 0.13um LL/FSG process
USB 2.0 PHY, UMC 0.13um LL Logic process....
79
0.118
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 PHY (Pure device mode), UMC 0.18um GII Logic RVT/FSG process....
80
0.118
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 Analog PHY, UMC 0.18um GII Logic RVT/FSG process....
81
0.118
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process...
82
0.118
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process...
83
0.118
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process...
84
0.118
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process...
85
0.118
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process
USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process...
86
0.118
USB 3.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
Crystal-less USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process....
87
0.118
USB 3.0 OTG PHY IP, UMC 40nm LP process
USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process....
88
0.118
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process...
89
0.118
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process...
90
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit...
91
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process...
92
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process...
93
0.118
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x005F_x005F_x005F_x005F_x000D_ cost down from FZOTG266HJ0C_A
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A...
94
0.118
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF...
95
0.118
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...
96
0.118
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process....
97
0.0
SD4.1 UHS- II PHY IP
SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consumption. This PHY IP is...
98
0.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
99
0.0
USB 2.0 PHY IBM 180
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
100
0.0
USB 2.0 PHY TSMC 40G
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
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